// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Tue May 24 14:50:49 2016

charge charge_inst
(
	.clk(clk_sig) ,	// input  clk_sig
	.rst_n(rst_n_sig) ,	// input  rst_n_sig
	.avs_wr_n(avs_wr_n_sig) ,	// input  avs_wr_n_sig
	.avs_writedate(avs_writedate_sig) ,	// input [31:0] avs_writedate_sig
	.avs_address(avs_address_sig) ,	// input  avs_address_sig
	.flag1(flag1_sig) 	// output [3:0] flag1_sig
);

